GPU database

WGP

Configuration

This compute unit implements the RDNA 1 architecture. It consists of 4 blocks, each containing the following execution units.

Data type Execution rate
FP32 32 lanes, executing one operation per cycle
FP16 32 lanes, executing 2 operations/cycle
INT32 32 lanes, executing one operation per cycle
FP64 2 lanes, executing one operation per cycle

Block diagram

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ASICs

The following ASICs are using this compute unit:

Cards

The following cards are built using this compute unit: