GPU database

SMM

Configuration

This compute unit implements the Maxwell 2 architecture. It consists of 4 blocks, each containing the following execution units.

Data type Execution rate
FP32 32 lanes, executing one operation per cycle
INT32 32 lanes, executing one operation per cycle
FP64 1 lane, executing one operation per cycle

Block diagram

ALU
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DP

ASICs

The following ASICs are using this compute unit:

Cards

The following cards are built using this compute unit: