GPU database

Turing SM

Configuration

This compute unit implements the Turing architecture.

FP32 4 processing units with 16 lanes
FP64 2 processing units with 1 lane
FP16 4 processing units with 16 lanes, 2 operations/cycle
INT32 4 processing units with 16 lanes
16-bit Tensor 4 processing units with 2 lanes, 128 operations/cycle

Block diagram

ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
INT32
FP64
FP64

ASICs

The following ASICs are using this compute unit:

Cards

The following cards are built using this compute unit: