nCU

Configuration

This compute unit implements the Vega architecture. It consists of 4 blocks, each containing the following execution units.

Data type	Execution rate
FP32	16 lanes, executing one operation per cycle
FP16	16 lanes, executing 2 operations/cycle
INT32	16 lanes, executing one operation per cycle
FP64	8 lanes, executing one operation per cycle

ALU

The following ASICs are using this compute unit:

The following cards are built using this compute unit: