VLIW5 SIMD Engine
Configuration
This compute unit implements the TeraScale 2 architecture. It consists of a single block with the following execution units.
| Data type | Execution rate |
| FP32 | VLIW unit with 16 lanes, executing 5 operations/cycle |
|---|---|
| INT32 | VLIW unit with 16 lanes, executing 5 operations/cycle |
Block diagram
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU