GPU database

SM

Configuration

This compute unit implements the Pascal (HPC) architecture. It consists of 2 blocks, each containing the following execution units.

Data type Execution rate
FP32 32 lanes, executing one operation per cycle
FP16 32 lanes, executing 2 operations/cycle
INT32 32 lanes, executing one operation per cycle
FP64 16 lanes, executing one operation per cycle

Block diagram

ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
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ALU
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ALU
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ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
DP
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
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ALU
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ALU
ALU
ALU
ALU
ALU
ALU
ALU
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ALU
ALU
DP
DP
DP
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DP
DP
DP
DP
DP
DP
DP
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DP

ASICs

The following ASICs are using this compute unit:

Cards

The following cards are built using this compute unit: