GPU database

SMX

Configuration

This compute unit implements the Kepler architecture. It consists of a single block with the following execution units. Additionally, this compute unit has multiple issue ports. Instructions scheduled onto separate issue ports can execute in parallel, but they require some instruction-level parallelism in the input.

Data type Issue port Execution rate
FP32 0, 1, 2, 3, 4, 5 32 lanes, executing one operation per cycle
INT32 0, 1, 2, 3, 4, 5 32 lanes, executing one operation per cycle
FP64 7, 8, 9, 10 16 lanes, executing one operation per cycle

Block diagram

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DP
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7
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10

ASICs

The following ASICs are using this compute unit:

Cards

The following cards are built using this compute unit: